Adesto And Cadence Collaborate To Strengthen IoT Device Flash Memory

  • The collaboration facilitates higher transfer rates and lower latency among IoT devices.
  • Other benefits include lower power consumption, lower cost of production and better system design.
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Flash memory devices in IoT systems require increasingly higher transfer rates and lower latency, as these products have increasingly become code-intensive with the rise of artificial intelligence (AI) processing.

To strengthen and enable this, Adesto Technologies Corporation and Cadence Design Systems, Inc. have collaborated to expand the ecosystem around the Expanded Serial Peripheral Interface (xSPI) communication protocol that supports higher transfer rates and lower latency for flash memory in the internet of things (IoT) devices. Expanding the flash SPI accesses from the traditional 4 I/Os (quad SPI) to 8 I/Os (octal SPI) with the xSPI serial synchronous protocol, increases the serial NOR flash throughput and provides a more efficient solution for emerging IoT applications.

“Support for new protocols, such as xSPI, is critical for standard adoption and will help enable a new class of IoT devices,” said David Peña, verification IP product management director, System & Verification Group at Cadence. “Cadence worked closely with Adesto and other JEDEC members to drive the development of the xSPI standard, and we’ve broadened our collaboration to facilitate ecosystem development. The availability of the memory model for Adesto’s EcoXiP and host controller design IP for xSPI devices enables joint customers to quickly and easily adopt xSPI while developing their products.”

Higher performance than quad SPI devices

Adesto’s EcoXiP NVM (Non-Volatile Memory) eliminates the need for expensive on-chip embedded flash in emerging IoT applications. By targetting power, system cost and performance, the NVM effectively brings down power consumption compared to other octal devices and offers higher performance than quad SPI devices.

“Moving intelligence to the edge can provide significant advantages, but heavier local processing means that architects must revisit their system’s memory architecture,” said Gideon Intrater, Adesto’s CTO. “xSPI makes it easier for system designers to reap the benefits of octal devices like EcoXiP for smarter, more efficient and user-friendly designs. The new Cadence memory model will help our EcoXiP customers to have even more optimized systems.”

Cadence memory model suite

The Cadence memory model for xSPI (part of the Cadence Verification Suite) is optimised for XceliumParallel Logic Simulation, along with supported third-party simulators. The suite comprises of best-in-class core engines and verification fabric technologies that support the Cadence Intelligent System Design strategy, enabling better SoC (System On Chip) design.