The Speedster7t FPGA family is specifically optimised for high-bandwidth workloads and features a high-density array of new machine learning processors (MLPs) blocks
Achronix Semiconductor Corporation, a leading company in FPGA-based hardware accelerator devices, announced the launch of an innovative, new FPGA family in order to meet the rising demands of artificial intelligence (AI), machine learning (ML) and high-bandwidth data acceleration applications.
Based on a highly optimised new architecture, the Achronix Speedster7t family goes beyond traditional FPGA solutions with ASIC-like performance, FPGA adaptability and improved functionality to streamline design, the company said in a statement.
The Speedster7t FPGA family is specifically optimised for high-bandwidth workloads. It features a new 2D network-on-chip (NoC), and a high-density array of new machine learning processors (MLPs) blocks that are optimised for high-bandwidth and AI/ML workloads.
By integrating FPGA programmability with ASIC routing structures and compute engines, the new solution can create a new FPGA+ class of technology.
Meeting requirements of high-performance market
Commenting on the development, Robert Blake, President and CEO, Achronix Semiconductor, said, “The growth potential for AI/ML is astounding and the use cases are rapidly evolving, and we are offering a new solution to address the varying requirements of high performance, flexibility and time to market.”
“Our Speedster7t family breaks new ground as the first solution to deliver FPGA adaptability with ASIC-like performance. We believe our new ‘FPGA+’ class of technology truly pushes the boundaries in the high-performance market,” he added.
While creating the Speedster7t family of FPGAs, the engineering team at Achronix reconsidered the complete FPGA architecture in order to balance on-chip processing, interconnect and external I/O, to enhance the throughput of data-intensive workloads like those found in server-based and edge-based AI/ML applications, networking and storage.
Speedster7t devices are manufactured on TSMC’s 7nm FinFET process and are designed to receive huge amount of data from many high-speed sources, distribute that data to the programmable on-chip algorithmic and processing units, and then provide the results with lowest possible latency. These include high-bandwidth GDDR6 interfaces, PCI Express Gen5 and 400G Ethernet ports – all interconnected to offer ASIC-level bandwidth, along with retaining the entire programmability of FPGAs.